Essays about: "Formal verification"

Showing result 16 - 20 of 82 essays containing the words Formal verification.

1. 16. Filtering equivalent changes from dependency updates with CBMC

   University essay from Blekinge Tekniska Högskola/Institutionen för datavetenskap

   Author : Jonas Mårtensson; [2022]
   Keywords : CBMC; change impact analysis; equivalence analysis; auto-generation; CBMC; konsekvensanalys; ekvivalensanalys; autogenerering;

   Abstract : Background. Open source dependencies have become ubiquitous in software development and the risk of regressions during an update are a key concern facing developers. Change impact analysis (CIA) can be used to assess the effects of a dependency update and aid in addressing this challenge. READ MORE

3. 17. Validation of efficiency of formal verification methodology for verification closure

   University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

   Author : Gautham Prabhakar; [2022]
   Keywords : UVM; formal verification; assertions; verification engineers; SVA; TLV; jasper gold; UVM; formell verifiering; assertions; verifierar; SVA; TLV; jasper gold;

   Abstract : Application Specific Integrated Circuits (ASIC) and Field Programmable Gate Arrays (FPGA) verification is quite a time consuming phase in design flow cycle and it can be done using methodologies such as Universal Verification Methodology (UVM) and formal verification.The UVM methodology is simulation based verification where in the verifier will have to trigger the Design Under Test (DUT) manually by writing sequences which target different features of the DUT and the verification environment can also have verification directives such as assertions to spot design bugs. READ MORE

4. 18. Energy efficient Ericsson Many-Core Architecture (EMCA) IP blocks for 5G ASIC

   University essay from Lunds universitet/Institutionen för elektro- och informationsteknik

   Author : Zilin Zhang; [2021]
   Keywords : Technology and Engineering;

   Abstract : Power consumption has become a leading concern for SoC aimed at 5G products that demand increased functionality, smaller form factors, and low energy footprint. For some EMCA IP blocks a hierarchical clock gating mechanism ensures coarse-grained power savings based on actual processing need but for many blocks this approach cannot be employed. READ MORE

5. 19. Automated inference of ACSL function contracts using TriCera

   University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

   Author : Jesper Amilon; [2021]
   Keywords : Formal Verification; Contract inference; Hoare Logic; Model Checking; Horn clauses; Formell verifikation; Kontraktgenerering; Formell semantik; Hoare logik; Modellprovning; Horn clauses;

   Abstract : This thesis explores synergies between deductive verification and model checking, by using the existing model checker TriCera to automatically infer specifications for the deductive verifier Frama-C. To accomplish this, a formal semantics is defined for a subset of ANSI C, extended with assume statements, called Csmall. READ MORE

6. 20. A Method for Porting Software Using Formal Specifications

   University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

   Author : Fredrik Öberg; Magnus Fredriksson; [2021]
   Keywords : porting; formal specification; TLA ; testing; Rust; portering; formell specifikation; TLA ; testning; Rust;

   Abstract : Formal specifications are mathematically based techniques with which a system can be analyzed, and its functionalities be described. Case studies have shown that using formal specifications can help reduce bugs and other inconsistencies when implementing a complex system; they are more likely found during the software design phase rather than later. READ MORE