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1. 1. Multilevel Gain Cell Arrays for Fault-Tolerant VLSI Systems

   University essay from Elektroniksystem

   Author : Muhammad Umer Khalid; [2011]
   Keywords : DRAM; SRAM; gain cell; multilevel; fault-tolerant; replica technique; finite state machine; PVT variations.;

   Abstract : Embedded memories dominate area, power and cost of modern very large scale integrated circuits system on chips ( VLSI SoCs). Furthermore, due to process variations, it becomes challenging to design reliable energy efficient systems. Therefore, fault-tolerant designs will be area efficient, cost effective and have low power consumption. READ MORE