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Showing result 1 - 5 of 12 essays matching the above criteria.
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1. Optimizing the instruction scheduler of high-level synthesis tool
University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)Abstract : With the increasing complexity of the chip architecture design for meeting different application requirements, the corresponding instruction scheduler of high-level synthesis tool needs to solve complex scheduling problems. Dynamically Reconfigurable Resource Array (DRRA) is a novel architecture based on Coarse-Grained Reconfigurable Architecture (CGRA) on SiLago platform, the instruction scheduler of Vesyla-II, the dedicated High-Level Synthesis (HLS) tool targets for DRRA needs to schedule the specific instruction sets designed for Distributed Two-level Control System (D2LC). READ MORE
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2. Develop a Graphical User Interface for the assembler for SiLago Platform
University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)Abstract : Vesyla-II is developed as the High-Level Synthesis (HLS) tool serving the SiLago platform. The assembler Manas is a part of the Coarse Grain Reconfigurable Architectures (CGRA) compiler in Vesyla-II, which is used to transform the information from source code into the target language. READ MORE
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3. The Global Interconnection Scheme of Silago : RTL Design and Verification
University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)Abstract : The Silago concept introduces a hardware-centric platform that is based on coarse-grained reconfigurable fabrics and networks on chips(NoCs). With the intra-region and inter-region NoC, the Silago platform can form resource clusters to host various applications. READ MORE
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4. Acoarse grain reconfigurable memory architecture for linear algebra and deep neural networks
University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)Abstract : Companies and institutions around the world have been working to develop machines with always more computing power. This race has now found its new objective: hexascale computing (with 1018 flops machines). READ MORE
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5. Design of the SiLago GNOC
University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)Abstract : Synchoros VLSI design style can be an alternative choice to fit the increasing complexity of embedded multi-processor architectures. SiLago Block is part of the synchoros blocks, which can effectively reduce the cost of logic and physical synthesis as it is hardened and highly centralized details from each layer of metal. READ MORE