Design of the SiLago GNOC

Abstract: Synchoros VLSI design style can be an alternative choice to fit the increasing complexity of embedded multi-processor architectures. SiLago Block is part of the synchoros blocks, which can effectively reduce the cost of logic and physical synthesis as it is hardened and highly centralized details from each layer of metal. Global NoCs play an essential part in system-level design and there is necessary to benchmark the SiLago global NoC against other existing NoC libraries. In this degree project, the structure of the NoC is established based on the SiLago models, including the wires and the switches. The whole structure has nine times nine grids and sixteen switches are placed inside symmetrically. The connection between two adjacent switches is built up by wires. The routing algorithm inside the switches can support the most common routing situations by destinations, routing states, and routing history. Except the routing algorithm, this essay provides some deadlock situations and also conclude some ways to solve them. The scripts developed from the NoC generator can be used to do the logical and physical synthesis for the SiLago models. The results from the synthesis can be explored to compare against other methods about the hability to estimate cost metrics from a high level of abstraction and the quality of results. The concept of partition is introduced to accomplish physical synthesis, and through this, the design can be more approach to the core idea of synchoros VLSI design.