Essays about: "Routing Algorithm and Deadlock"

Found 3 essays containing the words Routing Algorithm and Deadlock.

  1. 1. Design of the SiLago GNOC

    University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Author : Weiyao Tang; [2022]
    Keywords : Synchoros Blocks; SiLago models; Network on Chips; Routing Algorithm and Deadlock; Physical Design; Synchoros-block; SiLago-modeller; nätverk på chip; routingalgoritm och dödläge; fysisk design;

    Abstract : Synchoros VLSI design style can be an alternative choice to fit the increasing complexity of embedded multi-processor architectures. SiLago Block is part of the synchoros blocks, which can effectively reduce the cost of logic and physical synthesis as it is hardened and highly centralized details from each layer of metal. READ MORE

  3. 2. Extended Junction Based Source Routing Technique for Large Mesh Topology Network on Chip Platforms

    University essay from JTH, Data- och elektroteknik

    Author : Usman Mazhar Mirza; [2011]
    Keywords : Networks on Chip NoC ; System on Chip SoC ; Routing Algorithms; Source Routing; Junction Based Routing JBR ; Extended Junction Based Routing EJBR ; Packet Switched Networks; On Chip Communication; Core Based Design;

    Abstract : Network on Chip (NoC) has been proposed as a scalable and flexible interconnect infrastructure for communication among hundreds of cores on a core-based System on Chip. Routing algorithm affects the communication performance of a NoC. Therefore, many researchers have proposed different routing techniques in their work. READ MORE

  4. 3. EVALUATION OF SOURCE ROUTING FOR MESH TOPOLOGY NETWORK ON CHIP PLATFORMS

    University essay from JTH, Data- och elektroteknik

    Author : SAAD MUBEEN; [2009]
    Keywords : Network on Chip NoC ; System on Chip SoC ; Core Based Design; On Chip Communication; Distributed Routing; Source Routing; Routing Algorithms; Performance Analysis; Packet Switched Network; Specification and Description Language SDL ;

    Abstract : Network on Chip is a scalable and flexible communication infrastructure for the design of core based System on Chip. Communication performance of a NoC depends heavily on the routing algorithm. Deterministic and adaptive distributed routing algorithms have been advocated in all the current NoC architectural proposals. READ MORE