Deterministic Analysis of the Accuracy in FFT Hardware Architectures

Abstract: This Master Thesis studies the different quantization effects in hardware architecture due to the use of finite word lenght. This master thesis gives a deterministic analysis with relation to the accuracy and presents a relationship between input bits and coefficient bits for minimizing recourses and to obtained the best relation with the accuracy. Furthermore, the objective of this mater thesis is to find a direct relation between the input bits and coefficient bits. This can be used as guide for the design of FFT hardware architectures