Essays about: "ASIC digital circuit design."

Showing result 1 - 5 of 12 essays containing the words ASIC digital circuit design..

1. 1. Novel Method of ASIC interface IP development using HLS

   University essay from Lunds universitet/Institutionen för elektro- och informationsteknik

   Author : Anestis Athanasiadis; Chandranshu Mishra; [2023]
   Keywords : High Level Synthesis; HLS; Untimed C ; Control logic; I3C; clock-accurate design; IP development; Technology and Engineering;

   Abstract : High-Level Synthesis(HLS) is a design methodology that enables designers to implement hardware from high-level coding languages, such as C, C++, or System C. It provides designers with the ability to convey their design at a higher level of abstraction, which allows more emphasis on an algorithm and functional aspects of design instead on low-level hardware details. READ MORE

3. 2. Algorithmic Multi-Ported Memories Enabled Power-Efficient Pre-Distorter Design in ASIC

   University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

   Author : Xuying Shen; [2023]
   Keywords : Multi-ported memory; Digital Pre-distortion; Hardware design; ASIC; Power efficiency; Flerporterat minne; Digital Pre-distortion; Hårdvarudesign; ASIC; Effekteffektivitet;

   Abstract : The transition from the 5G to the 6G era is a pivotal juncture in contemporary wireless communication. Under such a circumstance, Digital Pre-Distortion (DPD) technology has established its significance as an effective method to linearize Power Amplifiers. READ MORE

4. 3. High Level Synthesis for ASIC and FPGA

   University essay from Lunds universitet/Institutionen för elektro- och informationsteknik

   Author : Malin Heyden; [2023]
   Keywords : HLS; high level synthesis; asic; fpga; catapult; filter; sfir; Technology and Engineering;

   Abstract : This thesis aims to evaluate the performance of Siemens’ High Level Synthesis (HLS) tool Catapult. HLS can be considered the next step up in abstraction level from writing traditional Register Transfer Level (RTL) code which is time consuming and error prone. READ MORE

5. 4. AXI-PACK : Near-memory Bus Packing for Bandwidth-Efficient Irregular Workloads

   University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

   Author : Chi Zhang; [2022]
   Keywords : General propose processor; on-chip bus protocol; irregular memory access; ASIC digital circuit design.; Generellt förslag på processor; on-chip-bussprotokoll; oregelbunden minnesåtkomst; digital ASIC-kretsdesign.;

   Abstract : General propose processor (GPP) are demanded high performance in dataintensive applications, such as deep learning, high performance computation (HPC), where algorithm kernels like GEMM (general matrix-matrix multiply) and SPMV (sparse matrix-vector multiply) kernels are intensively used. The performance of these data-intensive applications are bounded with memory bandwidth, which is limited by computing & memory access coupling and memory wall effect. READ MORE

6. 5. FPGA Implementation of the ORB Algorithm

   University essay from Lunds universitet/Institutionen för elektro- och informationsteknik

   Author : Xinyuan Zhang; Emil Sturk Sellstedt; [2022]
   Keywords : Technology and Engineering;

   Abstract : Image feature extraction has become a key technology in the field of autonomous Artificial Intelligence. The algorithm Oriented FAST and Rotated BRIEF (ORB), uses established technologies in image processing to allow a computer to ”see” and navigate its surroundings. READ MORE