Advanced search
Found 5 essays matching the above criteria.
-
1. A Digital Design Flow - From Concept to RTL Description, Using Mathworks and Cadence's Tools
University essay from Lunds universitet/Institutionen för elektro- och informationsteknikAbstract : This report presents our digital design flow for creating high speed very large scale integration circuits using a fifth generation disruptive beamforming control and data processing circuit as example. The flow consists of different stages. READ MORE
-
2. Spice Circuit Reduction for Speeding up Simulation and Verification
University essay from Lunds universitet/Institutionen för elektro- och informationsteknikAbstract : The focus of this work has been to implement a generic netlist reduction engine to speed up circuit simulations. The netlist reduction techniques are further optimized for Static Random-Access Memory (SRAM), wherein we exploit the repetitive pattern of the circuit. READ MORE
-
3. Formal Methods in Verification of Interface and Bus Protocols
University essay from KTH/Skolan för informations- och kommunikationsteknik (ICT)Abstract : This master thesis is performed on behalf of the Swedish technology company Ericsson and is meant to evaluate the efficiency of an assertion-based Verification Intellectual Property (abVIP) against an already existing constrained random Verification Intellectual Property (crVIP). The abVIP is a verification entity which is connected with a predefined design and proves that the design is adhering to the specification properties through conditional checks, which uses mathematical proofs rather than prolonged simulation based input stimuli. READ MORE
-
4. An On-Chip Memory for Testing of High-Speed Mixed-Signal Circuits
University essay from Elektroniska komponenter; Tekniska högskolanAbstract : Mixed-signal processing systems especially data converters can be reliably tested at high frequencies using on-chip testing schemes based on memory. In this thesis, an on-chip testing strategy based on shift registers/memory (2 k bits) has been proposed for digital-to-analog converters (DACs) operating at 5 GHz. READ MORE
-
5. Physical Planning of ASIC’s in mobile systems
University essay from Institutionen för systemteknikAbstract : With increasing demands in terms of timing, area and power, today’s ASIC (Application Specific Integrated Circuit) designers are faced with new problems as technology emerges. Ericsson has started to work in 65 nm and realized that the methods used in previous, larger technologies, does not offer good enough correlation between synthesis and the results after physical placement. READ MORE
