Design a Three-Stage Pipelined RISC-V Processor Using SystemVerilog

Abstract: RISC-V is growing in popularity as a free and open RISC Instruction Set Architecture (ISA) in academia and research. Also, the openness, simplicity, extensibility, and modularity, among its advantages, make it more and more used by designers in industry. The aim of this thesis is to design an open-source RISC-V processor. The development of this RISC-V processor was based on the prototype which was made in the course IL2232 Embedded Systems Design Project (SoI-CMOS Design group), against an experimental high-temperature SoC CMOS process. SystemVerilog was used for RTL coding. ModelSim was used for RTL simulation. Genus was used for digital synthesis and Innovus was used for digital place & route. The thesis concludes that this RISC-V processor can run the compiled C-code which has been produced by the virtual platform tool Imperas OVP. The instruction set RV32IM is the Instruction Set base for this processor. Through simulation, the CPI of this RISC-V processor can be collected while running different benchmark programs developed in two parallel Master thesis to this one. To a certain extent, it can reflect the performance of the processor. However, the actual execution time needs to be tested by loading the processor to the hardware. This part will not be discussed in this thesis but is left for future work. The gate count is collected by digital synthesis and the corresponding area is collected after digital place & route.