Essays about: "RTL simulation"

Showing result 1 - 5 of 15 essays containing the words RTL simulation.

1. 1. Modeling, Simulation, and Injection of Camera Images/Video to Automotive Embedded ECU : Image Injection Solution for Hardware-in-the-Loop Testing

   University essay from Uppsala universitet/Signaler och system

   Author : Anton Lind; [2023]
   Keywords : ADAS; AD; ADS; HIL; Hardware in the loop; Hardware-in-the-loop; ECU; VCU; Automotive; Embedded; System; Systems; Camera; Image; Video; Injection; FPGA; MPSoC; Vivado; Vitis; VHDL; Volvo; Cars; FMC; HPC; LPC; MIPI CSI2; GMSL2; AMBA AXI4; Xilinx; RTL; Implementation; Synthesis; Intelectual Property; IP; Vehicle computing unit; Electronic control unit; TEB0911; TEF0007; TEF0010; CSI2 Tx; CSI2 Tx Subsystem; Zynq; SerDes; AXI4; AXI4-Lite; Programmable Logic; PL; Processor System; PS; C; C ; Video test pattern generator; VTPG; Axi traffic generator; ATG; Ultrascale ; Virtual input output; VIO; Integrated logic analyzer; ILA; Interface Unit;

   Abstract : Testing, verification and validation of sensors, components and systems is vital in the early-stage development of new cars with computer-in-the-car architecture. This can be done with the help of the existing technique, hardware-in-the-loop (HIL) testing which, in the close loop testing case, consists of four main parts: Real-Time Simulation Platform, Sensor Simulation PC, Interface Unit (IU), and unit under test which is, for instance, a Vehicle Computing Unit (VCU). READ MORE

3. 2. Exploring Ethernet Switching Architectures for Area-Efficient Low-End Switches

   University essay from Lunds universitet/Institutionen för elektro- och informationsteknik

   Author : Jon Swedberg; Felix Ghosh; [2023]
   Keywords : Ethernet Switch; Architecture; Silicon Area; Area Optimization; ASIC; FPGA; Technology and Engineering;

   Abstract : The aim of this thesis project has been to develop an architecture for L2 ethernet switches that would be optimized for silicon area, targeting smaller low-end switches. A selection was made of three different switching architectures, which were compared and analyzed to explore the benefits and drawbacks of different approaches. READ MORE

4. 3. Design a Three-Stage Pipelined RISC-V Processor Using SystemVerilog

   University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

   Author : Ziyan He; [2022]
   Keywords : RISC; RISC-V; ISA; SystemVerilog; RTL simulation; RV32IM; CPI; RISC; RISC-V; ISA; SystemVerilog; RTL simulering; RV32IM; CPI;

   Abstract : RISC-V is growing in popularity as a free and open RISC Instruction Set Architecture (ISA) in academia and research. Also, the openness, simplicity, extensibility, and modularity, among its advantages, make it more and more used by designers in industry. The aim of this thesis is to design an open-source RISC-V processor. READ MORE

5. 4. A Digital Design Flow - From Concept to RTL Description, Using Mathworks and Cadence's Tools

   University essay from Lunds universitet/Institutionen för elektro- och informationsteknik

   Author : Tor Hammarbäck; Jorge Deza Concori; [2022]
   Keywords : Technology and Engineering;

   Abstract : This report presents our digital design flow for creating high speed very large scale integration circuits using a fifth generation disruptive beamforming control and data processing circuit as example. The flow consists of different stages. READ MORE

6. 5. Design parameterizable filter using High Level Synthesis

   University essay from Lunds universitet/Institutionen för elektro- och informationsteknik

   Author : Troels Maehl Folke; Wenqian Ding; [2021]
   Keywords : Technology and Engineering;

   Abstract : As the ASIC designs continue to grow in complexity, traditional RTL level of abstraction is becoming a productivity bottleneck. The RTL design process requires extensive time and effort for verification of algorithmic correctness as well as correct timing and interface behavior. READ MORE