Reconfigurable Instrument Access Network with a Functional Port Interface

Abstract: The ever-increasing need for higher performance and more complex functionality pushes the electronics industry to find a faster and more efficient way to test and debug an Integrated Circuit (IC). Currently, the IEEE Std. 1149.1, known as Joint Test Action Group (JTAG) is considered as state of the art by the industry. JTAG is used to perform debugging and testing through Test Access Port (TAP). However, the IEEE Std. 1149.1 standard has three major drawbacks, such as: • Lack of flexibility of hardware and scalability in scheduling the access to the instruments; • Boundary Scan Definition Language (BSDL), which is part of the JTAG standard, is insufficient to describe the myriad types of instruments present in an IC; • Absence of a language to ascertain the operation of an instrument independently of its position, configuration or utilization within an IC. Therefore, the IEEE Std. 1687, also known as Internal JTAG (IJTAG), was developed to mitigate these drawbacks by offering additional features, namely: • The Segment Insertion Bit (SIB) and ScanMux control bit are introduced for dynamic reconfiguration of a boundary scan path; • Procedural Description Language (PDL) and Instrument Connectivity Language (ICL) are used to fulfill the need for interfacing and description of an on-chip instrument of variable complexity. In this thesis, we proposed Universal Asynchronous Receiver Transmitter, known as UART, as a functional port to access embedded instruments and designed IJTAG network on Xilinx Field-Programmable Gate Array (FPGA) followed by implementation of the re-targeting tool in Python programming language. Our main objective was to determine if the TAP and the associated controller can be replaced by a JTAG port interface while maintaining the same functionality. Additionally, we used data transfer as a performance metric to determine the feasibility of the UART. We explored 4 different design alternatives by building a narrative from a pure software solution to full-featured hardware solution, consequently adding new components to efficiently interpret re-targeting commands, thereby optimizing data transfer and FPGA resource utilization. Finally, we made recommendations based on results obtained, as to inclusion or exclusion of the different components.