Evaluation of Divider and Linear Interpolation Architectures on FPGAs

Abstract: The Field Programmable Gate Array (FPGA) is a platform with a unique set offeatures. It combines the programmability of general purpose computers with the flexibility of Application Specific Integrated Circuits (ASIC). Most basic operations have been thoroughly studied on ASICs and the best architecture for each operation has often been found. This is not the case for FPGAs where often it is just assumed that the best architecture for an operation is the same in a FPGA as in a ASIC. As FPGAs have unique features and restrictions compared to ASICs this assumption is not always right. In this thesis, divider- and interpolation-architectures have been studied and modified to fit better on the FPGA platform. To do this a base design from the ASIC world was taken and studied to look for things that can be improved for the FPGA platform. These changes were then simulated and tested on four different FPGA-chip series for a wide range of bit lengths. For the divider architecture, it was found that the non-restoring divider design performed the best. For the interpolation architecture, some interesting ideas on how to save hardware was found but no real conclusion can be reached about which design is better than the others.