Investigation of 60 GHz Radio Front-ends in Nanometer CMOS
In the past few years, silicon mm-wave, especially 60GHz CMOS design has experienced a transition from an obscure topic to a research hot spot. The focus of this thesis is the design of a 60GHz receiver front-end integrated circuit, together with device modeling solutions, using 65nm CMOS technology.
A 60GHz to 5GHz heterodyne receiver topology is initially architected to exploit its possible compatibility with the 5GHz legacy WLAN system. In order to implement this frontend, an EM simulation based device modeling methodology together with the corresponding design flow has been proposed, which is tailored for the specific 65nm CMOS design kits and the available simulation tool. Based on thorough analysis of the process feature, efforts on device modeling for 60GHz operation have been taken. For active device, an EM model, using exiting transistor compact model as core, is developed for the NFET valid in vicinity of 60GHz to account for parasitic elements due to wiring stacks. Solutions for implementing the passive components in the specific circuit blocks have been illustrated. In particular, constructing, optimizing and physically characterizing of spiral inductor operating around 60GHz frequency band has been demonstrated. After the modeling efforts, a single-stage cascode LNA and a single-gate transconductance-pumped mixer are individually designed in the IBM 65nm CMOS process, characterized by EM co-simulation, and then compared with the state-of-the-art. Finally, the LNA and mixer has been integrated, layout and simulated as a complete front-end. The frontend achieves a conversion gain of 11.9dB and an overall SSB noise figure of 8.2dB, with an input return loss of -13.7dB. It consumes 6.11mW power, and its layout occupies a die area of 0.33×0.44mm2.
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