Using Approximate Computing Circuits to Optimize Power of an ASIC

Abstract: The growing demand for network cameras to support real-time image processing and machine-learning applications has created a need for low-power solutions. Although technology scaling makes complex computations feasible, voltage scaling is limited, leading to higher power density and dark silicon problems. One potential solution is the use of Approximate Arithmetic Circuits (AACs). This effectively reduces the number of logic gates required to perform arithmetic computations on ASICs. This technique is particularly suitable for image applications because the human eye’s perceptual tolerance makes a degree of error admissible. In this thesis, the Lanczos scaling is selected as the image application to evalu- ate the feasibility of applying AACs to trade off accuracy for power. To quantita- tively evaluate the impact on image quality introduced by AAC errors, arithmetic accuracy metrics and image quality metrics are studied to find a correlation be- tween them. Furthermore, power simulations are conducted on AACs using sub-10 nm technology to validate the power savings the chosen fabrication node achieves. Finally, the exact multipliers in the Lanczos scaling hardware are replaced with a selection of AACs, and then the system-level power consumption is assessed when scaling actual images. The outcome of this study shows that the image scaling application produces a power saving exceeding 50% while maintaining a high Structural Similarity Index Metric (SSIM) of up to 0.9. This finding contributes to understanding the potential of an AAC in reducing power consumption in image processing circuits, paving the way for future advancements in approximate computing techniques.