Essays about: "CLOCK IN VHDL"

Showing result 11 - 15 of 15 essays containing the words CLOCK IN VHDL.

  1. 11. DESIGN AND PROTOTYPE OF RESOURCE NETWORK INTERFACES FOR NETWORK ON CHIP

    University essay from JTH, Data- och elektroteknik

    Author : Adnan Mahmood; Zaheer Ahmed Mohammed; [2009]
    Keywords : Network on Chip NoC ; System on Chip SoC ; Resource Network Interface RNI ; Altera FPGA; Nios II Core; On Chip Communication; Distributed Routing; Source Routing;

    Abstract : Network on Chip (NoC) has emerged as a competitive and efficient communication infrastructure for the core based design of System on Chip. Resource (core), router and interface between router and core are the three main parts of a NoC. Each core communicates with the network through the interface, also called Resource Network Interface (RNI). READ MORE

  2. 12. Modelling and implementation of an MPEG-2 video decoder using a GALS design path.

    University essay from Institutionen för systemteknik

    Author : Kaj Rosengren; [2006]
    Keywords : GALS; Simulink; MPEG; IDCT; Huffman;

    Abstract : As integrated circuits get smaller, faster and can fit more functionality, more problems arise with wire delays and cross-talk. Especially when using global clock signals distributed over a large chip area. This thesis will briefly discuss a solution to this problem using the Globally Asynchronous Locally Synchronous (GALS) design path. READ MORE

  3. 13. Hardware bidirectional real time motion estimator on a Xilinx Virtex II Pro FPGA

    University essay from Institutionen för systemteknik

    Author : Rashid Iqbal; [2006]
    Keywords : Bidirectional motion estimation; FPGA; Relationally placed macro; CLB; slice; tristate buffers; comparator; pipelining; search upper; search lower; VHDL; Xilinx; block matching; MeEngine; LMC; CMC.; sum of absolute differences; systolic array; SARow; PE2X8; MeProC; 125 MHz; Virtex II Pro;

    Abstract : This thesis describes the implementation of a real-time, full search, 16x16 bidirectional motion estimation at 24 frames per second with the record performance of 155 Gop/s (1538 ops/pixel) at a high clock rate of 125 MHz. The core of bidirectional motion estimation uses close to 100% FPGA resources with 7 Gbit/s bandwidth to external memory. READ MORE

  4. 14. A Synthesizable VHDL Model of the Serial Communication Interface and Synchronous Serial Interface of Motorola DSP56002

    University essay from Institutionen för systemteknik

    Author : Swaroop Mattam; [2006]
    Keywords : VHDL model; SSI; SCI; Motorola DSP56002;

    Abstract : The design and implementation of a synthesizable model of the Serial Communication Interface and Synchronous Serial Interface, which constitutes the Port C of Motorola DSP56002 is presented in this report. They serves as a full duplex serial interface to other DSPs, processors, codecs, digital-to-analog and analog-to-digital converters and other transducers. READ MORE

  5. 15. System Design of RF Receiver and Digital Implementation of Control Logic

    University essay from Institutionen för teknik och naturvetenskap

    Author : Marcus Ström; [2003]
    Keywords : Electronics; Transceiver; receiver; RF; telemetry; modulation; coding; system design; digital implementation; VHDL; Verilog; RTL; low power consumption; LNA; detector and decoder.; Elektronik;

    Abstract : This report is the outcome of a thesis work done at Linköpings University, campus Norrköping. The thesis work was part of the development of a RF transceiver chip for implantable medical applications. The development was done in cooperation with Zarlink Semiconductor AB, located in Järfälla, Stockholm. READ MORE