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Showing result 1 - 5 of 21 essays matching the above criteria.

1. 1. Exploring Ethernet Switching Architectures for Area-Efficient Low-End Switches

   University essay from Lunds universitet/Institutionen för elektro- och informationsteknik

   Author : Jon Swedberg; Felix Ghosh; [2023]
   Keywords : Ethernet Switch; Architecture; Silicon Area; Area Optimization; ASIC; FPGA; Technology and Engineering;

   Abstract : The aim of this thesis project has been to develop an architecture for L2 ethernet switches that would be optimized for silicon area, targeting smaller low-end switches. A selection was made of three different switching architectures, which were compared and analyzed to explore the benefits and drawbacks of different approaches. READ MORE

3. 2. High Level Synthesis for ASIC and FPGA

   University essay from Lunds universitet/Institutionen för elektro- och informationsteknik

   Author : Malin Heyden; [2023]
   Keywords : HLS; high level synthesis; asic; fpga; catapult; filter; sfir; Technology and Engineering;

   Abstract : This thesis aims to evaluate the performance of Siemens’ High Level Synthesis (HLS) tool Catapult. HLS can be considered the next step up in abstraction level from writing traditional Register Transfer Level (RTL) code which is time consuming and error prone. READ MORE

4. 3. Design a Three-Stage Pipelined RISC-V Processor Using SystemVerilog

   University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

   Author : Ziyan He; [2022]
   Keywords : RISC; RISC-V; ISA; SystemVerilog; RTL simulation; RV32IM; CPI; RISC; RISC-V; ISA; SystemVerilog; RTL simulering; RV32IM; CPI;

   Abstract : RISC-V is growing in popularity as a free and open RISC Instruction Set Architecture (ISA) in academia and research. Also, the openness, simplicity, extensibility, and modularity, among its advantages, make it more and more used by designers in industry. The aim of this thesis is to design an open-source RISC-V processor. READ MORE

5. 4. A Digital Design Flow - From Concept to RTL Description, Using Mathworks and Cadence's Tools

   University essay from Lunds universitet/Institutionen för elektro- och informationsteknik

   Author : Tor Hammarbäck; Jorge Deza Concori; [2022]
   Keywords : Technology and Engineering;

   Abstract : This report presents our digital design flow for creating high speed very large scale integration circuits using a fifth generation disruptive beamforming control and data processing circuit as example. The flow consists of different stages. READ MORE

6. 5. Efficient High-level Synthesis Implementation of massive MIMO Processing on RFSoC

   University essay from Lunds universitet/Institutionen för elektro- och informationsteknik

   Author : Sijia Cheng; [2022]
   Keywords : Technology and Engineering;

   Abstract : Massive multiple-input multiple-output (MIMO) refers to a wireless access technology that equips base station (BS) with hundreds to thousands of antennas to serve tens of user equipment (UE) in the same time-frequency resource. These extensive antennas improve spectral and energy efficiency, but the detection algorithms tend to be more complex with operations, multiplications, and inversions on larger size matrix. READ MORE