Essays about: "decimation"
Showing result 16 - 20 of 24 essays containing the word decimation.
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16. FPGA Implementation of Flexible Interpolators and Decimators
University essay from Elektroniksystem; Tekniska högskolanAbstract : The aim of this thesis is to implement flexible interpolators and decimators onField Programmable Gate Array (FPGA). Interpolators and decimators of differentwordlengths (WL) are implemented in VHDL. The Farrow structure is usedfor the realization of the polyphase components of the interpolation/decimationfilters. READ MORE
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17. Tree-Structured Linear-Phase Nyquist FIR Filter Interpolators and Decimators
University essay from Elektroniksystem; Tekniska högskolanAbstract : The master thesis is based upon a new type of linear-phase Nyquist finitie impulse responseinterpolator and decimator implemented using a tree-structure. The tree-structure decreasesthe complexity, considerably, compared to the ordinary single-stage interpolator structure. READ MORE
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18. A study on the decimation stage of a Δ-Σ ADC with noise-shaping loop between the stages.
University essay from ElektroniksystemAbstract : The filter complexity in the multi-stage decimation system of a Δ-Σ ADC increases progressively as one moves to higher stages of decimation due to the fact that the input word length of the higher stages also increases progressively. The main motivation for this thesis comes from the idea of investigating a way, to reduce the input word length in the later filter stages of the decimation system which could reduce the filter complexity. READ MORE
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19. Single Channel Speech Enhancement Using Spectral Subtraction Based on Minimum Statistics
University essay from Blekinge Tekniska Högskola/Sektionen för ingenjörsvetenskapAbstract : Speech is an elementary source of human interaction. The quality and intelligibility of speech signals during communication are generally degraded by the surrounding noise. Corrupted speech signals need therefore to be enhanced to improve quality and intelligibility. READ MORE
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20. Design of a Digital Down Converter for LTE in an FPGA
University essay from Akademin för teknik och miljöAbstract : In thesis a Digital Down Converter (DDC) for Long Term Evolution (LTE) signals is designed. The DDC shall be implemented in hardware in a Field Programmable Gate Array (FPGA). For an FPGA the desired operating speed is high. The purpose of this thesis is therefore to determine if it is possible to design such a system. READ MORE