Essays about: "digital hardware synthesis"
Showing result 6 - 10 of 16 essays containing the words digital hardware synthesis.
-
6. Evaluation of high-level synthesis tools for generation of Verilog code from MATLAB based environments
University essay from Luleå tekniska universitet/Institutionen för system- och rymdteknikAbstract : FPGAs are of interest in the signal processing domain as they provide the opportunity to run algorithms at very high speed. One possible use case is to sort incoming data in a measurement system, using e.g. a histogram method. READ MORE
-
7. High-Level Synthesis for Efficient Design and Verification
University essay from Lunds universitet/Institutionen för elektro- och informationsteknikAbstract : Designing hardware using High Level Synthesis automates parts of the digital hardware design process. By automating the process control is passed from the designer to the tool, thus it is highly important that the tool generates high performance hardware in terms of area and speed. READ MORE
-
8. Implementation of an 8-bit Dynamic Fixed-Point Convolutional Neural Network for Human Sign Language Recognition on a Xilinx FPGA Board
University essay from Lunds universitet/Institutionen för elektro- och informationsteknikAbstract : The goal of this thesis work is to implement a convolutional neural network on an FPGA device with the capability of recognising human sign language. The set of gestures that the neural network can identify has been taken from the Swedish sign language, and it consists of the signs used for representing the letters of the Swedish alphabet (a.k.a. READ MORE
-
9. Performance Evaluation of MathWorks HDL Coder as a Vendor Independent DFE Generation
University essay from Lunds universitet/Institutionen för elektro- och informationsteknikAbstract : This thesis aims to evaluate MathWorks HDL (Hardware Descriptive Language) Coder and compare the results with designs produced by its vendor dependent counterparts. The focus is mainly on evaluate the design effort needed to close timing and to get optimal resource mapping for a selected design. READ MORE
-
10. Characterization, Clock Tree Synthesis and Power Grid Dimensioning in SiLago Framework
University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)Abstract : A hardware design methodology or platform is complete if it has the capabilities to successfully implement clock tree, predict the power consumption for cases like best and worst Parasitic Interconnect Corners (RC Corners), supply power to every standard cell, etc.This thesis has tried to solve the three unsolved engineering problems in SiLago design. READ MORE
