Essays about: "instruction scheduling"
Showing result 1 - 5 of 18 essays containing the words instruction scheduling.
-
1. Optimizing the instruction scheduler of high-level synthesis tool
University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)Abstract : With the increasing complexity of the chip architecture design for meeting different application requirements, the corresponding instruction scheduler of high-level synthesis tool needs to solve complex scheduling problems. Dynamically Reconfigurable Resource Array (DRRA) is a novel architecture based on Coarse-Grained Reconfigurable Architecture (CGRA) on SiLago platform, the instruction scheduler of Vesyla-II, the dedicated High-Level Synthesis (HLS) tool targets for DRRA needs to schedule the specific instruction sets designed for Distributed Two-level Control System (D2LC). READ MORE
-
2. Machine Learning-Based Instruction Scheduling for a DSP Architecture Compiler : Instruction Scheduling using Deep Reinforcement Learning and Graph Convolutional Networks
University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)Abstract : Instruction Scheduling is a back-end compiler optimisation technique that can provide significant performance gains. It refers to ordering instructions in a particular order to reduce latency for processors with instruction-level parallelism. READ MORE
-
3. The Global Interconnection Scheme of Silago : RTL Design and Verification
University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)Abstract : The Silago concept introduces a hardware-centric platform that is based on coarse-grained reconfigurable fabrics and networks on chips(NoCs). With the intra-region and inter-region NoC, the Silago platform can form resource clusters to host various applications. READ MORE
-
4. Register Caching for Energy Efficient GPGPU Tensor Core Computing
University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)Abstract : The General-Purpose GPU (GPGPU) has emerged as the predominant computing device for extensive parallel workloads in the fields of Artificial Intelligence (AI) and Scientific Computing, primarily owing to its adoption of the Single Instruction Multiple Thread architecture, which not only provides a wealth of thread context but also effectively hide the latencies exposed in the single threads executions. As computational demands have evolved, modern GPGPUs have incorporated specialized matrix engines, e. READ MORE
-
5. Hardware Acceleration in the Context of Motion Control for Autonomous Systems
University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)Abstract : State estimation filters are computationally intensive blocks used to calculate uncertain/unknown state values from noisy/not available sensor inputs in any autonomous systems. The inputs to the actuators depend on these filter’s output and thus the scheduling of filter has to be at very small time intervals. READ MORE
