Investigation of Analog Calibration Systems for Spurious Tone Suppression in Frequency Triplers

Abstract: The market for Wi-Fi receiver designs for latest Wi-Fi standards, that cover RF bands in the 2.4 GHz, 5 GHz and 6 GHz spectrum, require increasingly stringent power consumption limitations as more of the market is driven towards battery-powered devices. In order to meet those needs, it is crucial to explore different ways of reducing power consumption in various receiver blocks. One such power consumer can be the LO generating stage. As present standards require higher operating frequencies, circuit blocks such as frequency synthesizers, filters and amplifiers lead to increased power requirements in the receiver chain. In addition, issues such as spurious tones from inductive coupling, as well as IM2 and IM3 mixing products, may necessitate additional filtering stages, leading to stricter requirements for the remainder of the circuit. This thesis explores the possibility of reducing power consumption in the LO generation stage by implementing analog calibration schemes for a frequency synthesizer block, which would enable running the LO source at a lower frequency. The LO is then brought to the required frequency through the use of the Edge-Combining Delay-Locked Loop (EC DLL) based synthesizer. This would relax energy requirements in the LO stage, which can then be better used in the rest of the receiver chain. Two self-calibration systems are proposed for the synthesizer. A mathematical support is derived and explained, formulating expressions which help quantifying the expected synthesizer performance, denoted as Spur-to-Carrier Ratio (SCR). A design flow for optimal spurious performance in EC DLL is suggested. Then, a design for the calibration mechanisms is constructed and simulated in 22 nm CMOS technology. Specifications for the required performance are derived based on the IEEE802.11ax standard interferer scenarios and final results are discussed. The circuit is only realised as a proof-of-concept schematic de 800 mV. The final circuit improves the SCR performance by 7.7 dB with no significant power consumption requirements added to the EC DLL circuit. The worst-case, total calibration time required for spurious tones compensation is 75.21 microseconds. At the end, a conclusion is formulated regarding the feasibility of this approach.