On the Design of CMOS Integrated LMBA

Abstract: In this present world there is a huge requirement for high data rates and less powerconsumption in mobile networking. To achieve this one need to build a highly efficientpower amplifiers which is the most power consuming component in transmitterfront end. Most of the power amplifiers are highly efficient at higher output powerlevels and achieving the similar efficiency at average or back-off power levels is challenging.Efficient PA architectures have been proposed in recent decades and onesuch architecture is the Load Modulated Balanced Amplifier (LMBA). All the existingLMBA designs have been implemented using the discrete components and GaNbased PA’s using Transmission Line (TL) for base-station applications which has adisadvantage of larger footprint. The main purpose of this thesis is to implementthe same idea in CMOS by replacing the discrete components with their lumpedcounterparts. In this work cascode amplifiers biased in deep class AB were implementedas the main and control amplifiers of LMBA. The circuit was implementedin TSMC 0.18 μm process. With on-chip inductor losses, for LMBA with controlsource, at 9 dB back-off and at center frequency of 2 GHz, the PAE is 22% with outputpower of 17 dBm and at maximum power of 23 dBm the PAE was close to 32%while PAE was 16% without load modulation. For LMBA with control amplifier, at6 dB back-off, the PAE is 27% compared to 19% for a reference amplifier and withload modulation, maximum power of 25.6 dBm. For DLMBA with inductor lossesat 6 dB OBO, a PAE of 25.3% was achieved compared to 20.2% for a referenceamplifier without load modulation, and load optimized for peak PAE, a absolutePAE improvement of 5.1% or a relative PAE improvement of 25.2%.