Phase Locked Loops in Fully Integrated NB-IoT Transceivers
Abstract: This thesis investigates how to fulfill the Narrow Band - Internet of Things (NB-IoT) specification for a fully integrated transceiver in the phase locked loop's (PLL) perspective. Designing a fully integrated transceiver, integrating a power amplifier (PA) is challenging as it leads to frequency pulling of the voltage controlled oscillator (VCO) in the PLL, deteriorating the performance. By increasing the bandwidth of the PLL, the frequency pulling can be suppressed, especially when the bandwidth is increased to at least twice the baseband bandwidth. The frequency pulling can be further suppressed by designing the PA balun in such a way that a common mode current cancels as well as designing the VCO inductor in an eight shape fashion, reducing the coupling from balun to inductor. The NB-IoT specification is extracted from 3GPP and translated to a phase noise requirement for the PLL and a parameterization of the PLL is made to ease the evaluation of the phase noise performance.
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