Development of a Light Weight L2-Cache Controller

Abstract: An L2 cache is a device that buffers data in fast memory closer to the Central Processing Unit(CPU) in order to deliver its contents with much lower latency than can otherwise be achieved bymain memory. This provides a substantial performance increase in many systems as the memoryinterface is often a bottleneck. The goal of this thesis is to develop a simple L2 cache usingVHDL for Cobham Gaisler’s open source hardware library GRLIB which currently lacks such acore. The outcome of the thesis is the IP core L2C-Lite which will be released in Febuary of 2022 as an addition to GRLIB. L2C-Lite has been integrated into multiple systems and has providedmajor performance gains in applications running under linux as well as other benchmarks. Inaddition, some potential improvements have been identified to further increase the performanceof the cache, as well as improve its usability in systems.