Simulating Energy-Efficient Hardware The Software Out-of-order Processor

Abstract: The modern trends for technology scaling are not extremely bright. The cost of transistors have leveled off recently, effectively halting the ability to put additional transistors on a chip for the same price. In addition, Dennard Scaling, what has allowed for switching additional transistors whilst scaling to smaller nodes isslowing significantly. This thesis, with focus on the hardware, proposes anenhanced stall-on-use in-order core hardware/software co-design which improves performance and energy efficiency by allowing out-of-program-order executionthrough allowing the hardware and software to communicate with one another --allowing the hardware to make dynamic decisions on how to direct execution flowto expose additional memory- and instruction level parallelism.The results are very promising where we see an increase in both performance (upto 3.7x speedup) and energy efficiency (up to 59% increase). While additional worki is needed to evaluate the extent of the benefits across a wide range of applications, SWOOP looks to be a good option for energy efficiency without compromisingperformance for memory-bound applications with MLP.