Essays about: "0.35 CMOS design THESIS"

Showing result 1 - 5 of 7 essays containing the words 0.35 CMOS design THESIS.

  1. 1. Integrated CMOS Doppler Radar : System Specification & Oscillator Design

    University essay from Linköpings universitet/Elektroniska Kretsar och System

    Author : Shampa Biswas; [2016]
    Keywords : CMOS oscillator circuit design;

    Abstract : This thesis report presents system specification, such as frequency and output power level, and selection topology of an oscillator circuit suitable for a CMOS Integrated Doppler radar application, in order to facilitate short range target detection within 5-15 m range, using a 0.35 μm CMOS process. READ MORE

  2. 2. Frame rate limiter for export restricted cameras

    University essay from Elektroniska komponenter; Tekniska högskolan

    Author : Saad Zulkifl; [2012]
    Keywords : ;

    Abstract : This master thesis describes the design of a low power and low noise CMOS circuit capable of limiting 9 frames per second. This is a part of a larger ongoing project for development and design of a low-cost IR night-vision network camera. This circuit is implemented in 0.35μm process. READ MORE

  3. 3. Study of CMOS Rectifers for Wireless Energy Scavenging

    University essay from Elektroniska komponenter; Tekniska högskolan

    Author : Aiysha Khalifa; [2010]
    Keywords : Energy Scavenging; Rectifier;

    Abstract : In recent years, there has been recent increase in the deployment of wireless sensor networks. These sensors are typically powered by a battery which has limited life span. READ MORE

  4. 4. Design of a High-Speed CMOS Comparator

    University essay from Institutionen för systemteknik

    Author : Ahmad Shar; [2007]
    Keywords : Comparator; CMOS comparator; Sigma-delta ADC; Low power design; High-speed.;

    Abstract : This master thesis describes the design of high-speed latched comparator with 6-bit resolution, full scale voltage of 1.6 V and the sampling frequency of 250 MHz. The comparator is designed in a 0.35 9m CMOS process with a supply voltage of 3. READ MORE

  5. 5. Design of a High Speed AGC Amplifier for Multi-level Coding

    University essay from Institutionen för systemteknik

    Author : Iftekharul Karim Bhuiya; [2006]
    Keywords : Broadband amplifier; high speed amplifier; 4-PAM Signaling; multi-level signaling; AGC amplifier; automatic gain control; shunt-shunt feedback; wideband amplifier;

    Abstract : This thesis presents the design of a broadband and high speed dc-coupled AGC amplifier for multi-level (4-PAM) signaling with a symbol rate of 1-GS/s ( 2-Gb/s ) . It is a high frequency analog design with several design challenges such as high -3 dB bandwidth ( greater than 500 MHz ) and highly linear gain while accommodating a large input swing range ( 120 mVp-p to 1800 mVp-p diff. READ MORE