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1. 1. Short Message Network-On-Chip Interconnect for ASIC

   University essay from KTH/Skolan för informations- och kommunikationsteknik (ICT)

   Author : Ejaz Sadiq; [2014]
   Keywords : ;

   Abstract : The rise of large scale integration has resulted in large number of processing elements/cores on a single ASIC. Thus an efficient interconnect scheme between the different processing elements and interfaces is required. Bus based interconnect poses problems such as non-scalability. READ MORE