Essays about: "Extended Gate"

Showing result 1 - 5 of 13 essays containing the words Extended Gate.

  1. 1. Towards Water Resource Recovery Facilities : Environmentally Extended Techno-Economic Assessment of Emerging Sewage Sludge Management Technologies in Sweden

    University essay from KTH/Hållbar utveckling, miljövetenskap och teknik

    Author : Harry Tibbetts; [2023]
    Keywords : Circular Economy; Waste Valorisation; Systems Analysis; LCA; MFA; EFA; TEA; Hydrothermal Carbonisation; Cirkulär ekonomi; Waste Valorisation; Systems Analysis; LCA; MFA; EFA; TEA; Hydrotermal Carbonization;

    Abstract : Municipal sewage sludge (MSS) management varies widely between countries and legislative regimes. Within the European directive for sewage treatment France applies over half of MSS to arable land, while The Netherlands has banned the practice (Kelessidis et al, 2012). READ MORE

  3. 2. A Simulation-Based Decision Support Tool for Circularity : Remanufacturing of an Electric Machine Case Study

    University essay from KTH/Produktionsutveckling

    Author : Mayari Pérez Tay; [2023]
    Keywords : Simulation; remanufacturing; circular business; electric machine;

    Abstract : Over the last years, environmental concerns have grown regarding the pressure manufacturing activities exerts on natural resources. Many materials have been classified by the EU as scarce, rare earth elements found in magnets are amongst critical materials with high supply risk. READ MORE

  4. 3. Aligning the Innovation Process Routines With Organizational Agility : A Case Study of a Healthcare Firm

    University essay from Högskolan i Halmstad/Akademin för företagande, innovation och hållbarhet

    Author : Constantin Catalin Ciorascu; Mohammad Alipanahi; [2023]
    Keywords : Organizational Agility; Innovation Process Routines; Types of Innovations; Healthcare; Medical Device;

    Abstract : Introduction: Traditional organizational routines for the innovation process, like the Stage-Gate Model, are often characterized by rigid and inflexible activities, limiting firms' ability to identify, develop, and commercialize software and digital/connected products and services. Examples of inflexible activities include predefined project milestones, linear progression through development stages, and a lack of iterative feedback loops. READ MORE

  5. 4. Implementation of Bolt Detection and Visual-Inertial Localization Algorithm for Tightening Tool on SoC FPGA

    University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Author : Muhammad Ihsan Al Hafiz; [2023]
    Keywords : Bolt detection; Visual-Inertial localization; System-on-Chip SoC ; Field-Programmable Gate Array FPGA ; Machine learning; Perspective-n-Points; Error-State Extended Kalman Filter ESEKF ; High-Level Synthesis HLS ; YOLO; Tightening tool; Bultdetektering; visuell-tröghetslokalisering; System-on-Chip SoC ; Field-Programmable Gate Array FPGA ; Machine Learning; Perspective-n-Points; Error-State Extended Kalman Filter ESEKF ; High-Level Synthesis HLS ; YOLO; åtdragningsverktyg;

    Abstract : With the emergence of Industry 4.0, there is a pronounced emphasis on the necessity for enhanced flexibility in assembly processes. In the domain of bolt-tightening, this transition is evident. Tools are now required to navigate a variety of bolts and unpredictable tightening methodologies. READ MORE

  6. 5. Validation of efficiency of formal verification methodology for verification closure

    University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Author : Gautham Prabhakar; [2022]
    Keywords : UVM; formal verification; assertions; verification engineers; SVA; TLV; jasper gold; UVM; formell verifiering; assertions; verifierar; SVA; TLV; jasper gold;

    Abstract : Application Specific Integrated Circuits (ASIC) and Field Programmable Gate Arrays (FPGA) verification is quite a time consuming phase in design flow cycle and it can be done using methodologies such as Universal Verification Methodology (UVM) and formal verification.The UVM methodology is simulation based verification where in the verifier will have to trigger the Design Under Test (DUT) manually by writing sequences which target different features of the DUT and the verification environment can also have verification directives such as assertions to spot design bugs. READ MORE