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Found 2 essays matching the above criteria.

1. 1. Optimizing the instruction scheduler of high-level synthesis tool

   University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

   Author : Zihao Xu; [2023]
   Keywords : Instruction scheduling; Scheduling algorithm; CGRA; High-level Sythnesis; SiLago; Algorithm-level Synthesis; Constraint programming; Instruktion schemaläggning; schemaläggning algoritm; CGRA; High-level Sythnesis; SiLago; Algoritm-nivå Synthesis; Constraint programmering;

   Abstract : With the increasing complexity of the chip architecture design for meeting different application requirements, the corresponding instruction scheduler of high-level synthesis tool needs to solve complex scheduling problems. Dynamically Reconfigurable Resource Array (DRRA) is a novel architecture based on Coarse-Grained Reconfigurable Architecture (CGRA) on SiLago platform, the instruction scheduler of Vesyla-II, the dedicated High-Level Synthesis (HLS) tool targets for DRRA needs to schedule the specific instruction sets designed for Distributed Two-level Control System (D2LC). READ MORE

3. 2. Develop a Graphical User Interface for the assembler for SiLago Platform

   University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

   Author : Yuxuan Wang; [2023]
   Keywords : Graphic intermediate representation; Graphical analytic system; High-level synthesis tool; Grafisk mellanrepresentationen; Grafiskt analytiskt system; Högnivå syntes verktyg;

   Abstract : Vesyla-II is developed as the High-Level Synthesis (HLS) tool serving the SiLago platform. The assembler Manas is a part of the Coarse Grain Reconfigurable Architectures (CGRA) compiler in Vesyla-II, which is used to transform the information from source code into the target language. READ MORE