Essays about: "RTL code"

Showing result 16 - 20 of 21 essays containing the words RTL code.

  1. 16. High Level Synthesis of FPGA-Based Digital Filters

    University essay from Uppsala universitet/Institutionen för informationsteknologi

    Author : Gerald Baguma; [2014]
    Keywords : ;

    Abstract : This thesis work is aimed at the high level synthesis of FPGA based IIR digital filters using Vivado HLS produced by Xilinx and HDL coder produced by MathWorks. The Higher Layer Model of the filter was designed in Vivado HLS, MATLAB and Simulink. Simulations, verification and Synthesis of the RTL code was done for both tools. READ MORE

  2. 17. Development of the NoGAP CL Hardware Description Language and its Compiler

    University essay from Institutionen för systemteknik

    Author : Carl Blumenthal; [2007]
    Keywords : NoGAP; HDL; processor; compiler;

    Abstract : The need for a more general hardware description language aimed specifically at processors, and vague notions and visions of how that language would be realized, lead to this thesis. The aim was to use the visions and initial ideas to evolve and formalize a language and begin implementing the tools to use it. READ MORE

  3. 18. Functional Self-Test of DSP cores in a SOC

    University essay from KTH/Mikroelektronik och Informationsteknik, IMIT

    Author : Sarmad Jamal Dahir; [2007]
    Keywords : functional testing; SOC; DSP; Self test; Embedded systems testing;

    Abstract : The rapid progress made in integrating enormous numbers of transistors on a single chip is making it possible for hardware designers to implement more complex hardware architectures in their designs. Nowadays digital telecommunication systems are implementing several forms of SOC (System-On-Chip) structures. READ MORE

  4. 19. HDL code analysis for ASICs in mobile systems

    University essay from Institutionen för systemteknik

    Author : Fredrik Wickberg; [2007]
    Keywords : HDL Spyglass RTL netlist lint constraints CDC DFT;

    Abstract : The complex work of designing new ASICs today and the increasing costs of time to market (TTM) delays are putting high responsibility on the research and development teams to make fault free designs. The main purpose of implementing a static rule checking tool in the design flow today is to find errors and bugs in the hardware definition language (HDL) code as fast and soon as possible. READ MORE

  5. 20. RTL implementation of Viterbi Decoder

    University essay from Institutionen för systemteknik

    Author : Wei Chen; [2006]
    Keywords : baseband FEC Viterbi Decoding;

    Abstract : A forward error correction technique known as convolutional coding with Viterbi decoding was explored in this final thesis. This Viterbi project is part of the baseband Error control project at electrical engineering department, Linköping University. In this project, the basic Viterbi decoder behavior model was built and simulated. READ MORE