Essays about: "field-programmable gate array"

Showing result 11 - 15 of 72 essays containing the words field-programmable gate array.

1. 11. FPGA Accelerated Digital Image Correlation For Clamping Force Measurement

   University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

   Author : János Csanád Csuvarszki; [2023]
   Keywords : Digital image correlation; Field-programmable gate array; High-level synthesis;

   Abstract : Digital image correlation is a contactless optical method used for displacement and strain measurement which has become increasingly popular in the field of experimental mechanics. A specialized use case for the algorithm is to measure the clamping force in bolted joints, a crucial metric when considering the longevity and reliability of the constructs. READ MORE

3. 12. Evaluating the performance of FPGA-based Secure Hash Algorithms for use in SPHINCS+

   University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

   Author : Kei Duke-Bergman; Alexander Huynh; [2023]
   Keywords : Bachelor’s thesis; FPGA; SHA; Cryptography; Kandidatexamensarbete; FPGA; SHA; Kryptografi;

   Abstract : In the digital landscape of today, large amounts of transactions, messaging and different kinds of authorizations are carried out online. To ensure the the integrity and security of these systems, digital signature systems are used to verify the identity of different individuals and entities. READ MORE

4. 13. High Level Synthesis for ASIC and FPGA

   University essay from Lunds universitet/Institutionen för elektro- och informationsteknik

   Author : Malin Heyden; [2023]
   Keywords : HLS; high level synthesis; asic; fpga; catapult; filter; sfir; Technology and Engineering;

   Abstract : This thesis aims to evaluate the performance of Siemens’ High Level Synthesis (HLS) tool Catapult. HLS can be considered the next step up in abstraction level from writing traditional Register Transfer Level (RTL) code which is time consuming and error prone. READ MORE

5. 14. Implementation of Bolt Detection and Visual-Inertial Localization Algorithm for Tightening Tool on SoC FPGA

   University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

   Author : Muhammad Ihsan Al Hafiz; [2023]
   Keywords : Bolt detection; Visual-Inertial localization; System-on-Chip SoC ; Field-Programmable Gate Array FPGA ; Machine learning; Perspective-n-Points; Error-State Extended Kalman Filter ESEKF ; High-Level Synthesis HLS ; YOLO; Tightening tool; Bultdetektering; visuell-tröghetslokalisering; System-on-Chip SoC ; Field-Programmable Gate Array FPGA ; Machine Learning; Perspective-n-Points; Error-State Extended Kalman Filter ESEKF ; High-Level Synthesis HLS ; YOLO; åtdragningsverktyg;

   Abstract : With the emergence of Industry 4.0, there is a pronounced emphasis on the necessity for enhanced flexibility in assembly processes. In the domain of bolt-tightening, this transition is evident. Tools are now required to navigate a variety of bolts and unpredictable tightening methodologies. READ MORE

6. 15. FPGA accelerated packet capture with eBPF : Performance considerations of using SoC FPGA accelerators for packet capturing.

   University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

   Author : Jakub Duchniewicz; [2022]
   Keywords : Field Programmable Gate Array; Acceleration; Networking; Embedded Linux; Field Programmable Gate Array; Field Programmable Gate Array; Acceleration; Nätverksarbete; Inbyggd Linux; sprzętowa akceleracja; sieci internetowe; wbudowany system Linux;

   Abstract : With the rise of the Internet of Things and the proliferation of embedded devices equipped with an accelerator arose a need for efficient resource utilization. Hardware acceleration is a complex topic that requires specialized domain knowledge about the platform and different trade-offs that have to be made, especially in the area of power consumption. READ MORE