Low-power Acceleration of Convolutional Neural Networks using Near Memory Computing on a RISC-V SoC

Abstract: The recent peak in interest for artificial intelligence, partly fueled by language models such as ChatGPT, is pushing the demand for machine learning and data processing in everyday applications, such as self-driving cars, where low latency is crucial and typically achieved through edge computing. The vast amount of data processing required intensifies the existing performance bottleneck of the data movement. As a result, reducing data movement and allowing for better data reuse can significantly improve the efficiency. Processing the data as closely to the memory as possible, commonly known as near-memory computing, increases the power efficiency and can significantly re- duce the bottleneck in the data movement. However, maintaining a low power consumption while at the same time being able to process large amounts of data is a challenge. The RISC-V Instruction Set Architecture (ISA) was designed for efficient and dense instruction encoding, enabling lower power consumption and quicker execution time. Extending the simple RISC-V ISA with specific instruc- tions for applications like image recognition can make a processor energy-efficient but less versatile than a conventional CISC processor. Codasip, a company specializing in RISC-V processors, offers a toolset for exploring and customizing processor architectures, through their proprietary C-based hardware description language, CodAl, which is used to generate SDK, HDL, and UVM within the Co- dasip Studio Environment. Codasip provides a selection fully configurable RISC-V cores, tailored for either low-power, and high-performance application. In this thesis we use a combination of high-level synthesis tools and EDA soft- ware to simplify design space exploration of accelerators, allowing for the accel- erators to be integrated as Near Memory Computing (NMC) accelerators on a customized RISC-V System on chip (SoC), for both Application Specific Inte- grated Circuits (ASIC) and Field Programmable Gate Arrays (FPGA). The flow contains implementation of custom instructions as well as a generic flow from Register Transfer Level (RTL) to GDSII for reuse in future works.