Distributed Memory Architecture with Hardware Graph Array for Configuring the Network Interconnections.

Abstract: The Network-on-chip is considered to be a promising architecture with the advent of increase in the integration of the distributed processing elements. The conflict of data transfer through the network became an urgent issue that need to be solved. DiMArch is an existing distributed memory architecture that can solve the data transfer conflict at compile time. This thesis extends DiMArch with a centralized Network-on-Chip manager called HDiMArch, this architecture monitor the memory accessibility and create data interconnection path with hardware. The conflict which occurred at runtime is resolved by establish the Hardware graph array. The HDiMArch is synthesized using TSMC 90nm with different parameters. Area, power and maximum power results are analyzed.