Investigation of using a PRET processor on a low-cost, low- power FPGA

Abstract: Mixed-criticality is a current trend in real-time embedded systems, where software tasks are integrated onto fewer hardware platforms. The basic idea is to use one processor to execute multiple tasks with differing requirements of certification, importance or safety. In systems where time is an important key factor the behavior of that system must be predictable at all times, which is hard to achieve when optimizations made to achieve good performance lower predictability at the same time. In 2007 Stephen A. Edwards and Edward A. Lee made a case for the precision-timed (PRET) machine as a solution, arguing that temporal behavior is to be treated equal to functional behavior. One of those PRET machines is FlexPRET, which is the processor we are studying in this thesis. This thesis aims to study the generation, synthesis and programming of FlexPRET, a finegrained multithreaded RISC-V based PRET processor developed at UC Berkeley. This is part of a larger-scale project to port FlexPRET to be used as a node processor in a NoC mesh generated by ForSyDe, a programming methodology developed at the Royal Institute of Technology.Previous synthesis of FlexPRET has been done on FPGAs from the Virtex-5 and Spartan-6 families by Xilinx. The FPGA used for this thesis is from the Cyclone IV family by Altera. Evaluation of the synthesis results have been performed by running a real-time application on FlexPRET that blinks LEDs on the Altera DE2-115 board.