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1. 1. Global clock distribution in the SiLago platform

   University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

   Author : Jordi Altayó; [2020]
   Keywords : ;

   Abstract : The extreme evolution of Very Large Scale Integration (VLSI) design has followed Moore’s law for the past decades, which predicts a doubling of the number of transistors that can be implemented on a chip every 18 months. However, tightly coupled with the evolution of the technology capabilities, the complexity during the implementation of such designs has also increased dramatically. READ MORE