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Showing result 1 - 5 of 33 essays matching the above criteria.
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1. The Global Interconnection Scheme of Silago : RTL Design and Verification
University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)Abstract : The Silago concept introduces a hardware-centric platform that is based on coarse-grained reconfigurable fabrics and networks on chips(NoCs). With the intra-region and inter-region NoC, the Silago platform can form resource clusters to host various applications. READ MORE
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2. Mapping DNNs onto the NoC Platform
University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)Abstract : This thesis uses an existing NoC simulation platform to construct a Network on Chip-based many-core system. The network is an 8_8 mesh topology. This thesis chooses LeNet5, ResNet, VGGNet, and AlexNet as the computing load, and tries to obtain a deep neural network mapping algorithm based on a NoC design method that can be widely used. READ MORE
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3. NoC for Versatile Micro-Code Programmable Multi-Core Processor Targeting Convolutional Neural Networks
University essay from Linköpings universitet/DatorteknikAbstract : This thesis investigates building a network-on-chip for a multi-core chip computing convolutional neural networks (CNNs) using Imsys processors in a tree architecture. The division of work on a multi-core chip is investigated. READ MORE
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4. A Specification for Time-Predictable Communication on TDM-based MPSoC Platforms
University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)Abstract : Formal System Design (ForSyDe) aims to bring the design of multiprocessor systems-on-chip (MPSoCs) to a higher level of abstraction and bridge the abstraction gap by transformational design refinement. The current research is focused on a correct-by-construction design flow, which requires design space exploration including formal models of computation and timepredictable platforms. READ MORE
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5. Global clock distribution in the SiLago platform
University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)Abstract : The extreme evolution of Very Large Scale Integration (VLSI) design has followed Moore’s law for the past decades, which predicts a doubling of the number of transistors that can be implemented on a chip every 18 months. However, tightly coupled with the evolution of the technology capabilities, the complexity during the implementation of such designs has also increased dramatically. READ MORE
