Configurable, scalable single-ended sense amplifier with additional auxiliary blocks for low-power two-port memories in advanced FinFET technologies

Abstract: System on Chip (SoC) designs contain a variety of Intellectual Property (IP) cores, including digital signal processing blocks, media and graphics processing units, as well as processing core units that employ multiple-port memories to enhance performance and bandwidth. These memories allow parallel read/write operations from the same memory blocks from different ports. Due to the enormous number of on-chip memories in modern SoCs, area efficiency is critical. Going down the technology node of transistors to create these memories is one solution to reduce the area and increase the computational density. However, as transistors were continuously scaled-down, lesser gate control and higher leakage current became a major concern. This led the semiconductor industry to reinvent the underlying transistor architecture and manufacturing processes. Today, Fin Field Effect Transistor (FinFET) are the world’s pioneering transistors commercially available in the market. These are multigate transistors designed primarily for high-speed/high-density applications, that could effectively increase gate control. In addition to area and power constraints, improving access time has always been a challenge in memories. Sense amplifiers are read circuit elements that are employed to interpret data bit stored in memory by amplifying a low-power bit line signal to recognizable logic levels, thereby improving the read access time. The goal of this thesis project is to use state-of-the-art finFET technology to design a low-power, configurable and compiler-friendly single-ended sense amplifier that can be easily scaled up or down based on the size of the memory block. This design dynamically produces reference voltage based on charge redistribution from high bit-line capacitance to low capacitance nodes. Apart from the single-ended sense amplifier, other memory sub-blocks like D Flip-flop, multiplexer and differential sense amplifier was also designed. The designed circuits also had to be verified before and after the layout phase, to understand the effects of parasitics in the design. The design verification flow was automized using a python script that performs statistical analysis on transistor parameter variations and accumulates the results of the simulation tests and evaluates the failure probability. The thesis project was carried out in Xenergic AB.