Methodology For Improving performance & Reliability In Low Voltage on-chip Memories

Abstract: Recent surveys show that on average about 70% of the area budget of the system on chip (SoC) is occupied by Static Random Access Memory (SRAM)s, with a capacity ranging from a few kilo-bits to tens of megabits. SRAM (static RAM or SRAM) is a type of electronic memory that uses bistable latching circuitry (flip-flop) to store each bit. SRAM is volatile in the conventional sense that data is eventually lost when the memory is not powered. The term static differentiates SRAM from DRAM (dynamic random-access memory) which must be periodically refreshed. SRAM is faster and more expensive than DRAM; it is typically used for CPU cache while DRAM is used for a computer's main One critical issue in modern SoCs when using such huge amount of on-chip memories is area efficiency. The other vital factor is power consumption. One desired approach in designing memories is to reduce power consumption by lowering the voltage but pay as little as possible in terms of silicon area overhead. Low-power memory design is a challenging eld that designers need to push the energy and area efficiency to extreme limits. In this thesis, the main goal will be to look into different approaches or techniques on how to maintain the low power SRAM memories functionality in terms of R/W reliability in low voltage operations. One useful technique is to be able to temporarily boost the voltage locally for desired nodes in the circuit without having to raise the operational SRAM supply voltage. So, a specially designed in-memory charge pump would be beneficial with the condition that the intrinsic large parasitic capacitances already existing on the memory is exploited for this purpose; hence keeping area overhead to a minimum. One other limitation in low voltage SRAMs is the sense amplifier. These circuits elements are generally working well with the nominal SRAM voltages verified for a certain technology node. However, special considerations require when the intention is to reduce the supply voltage. This requires to take a fresh look into sense amplifier implementations and propose a more suitable approach regarding theses elements of SRAM memories in low voltages. This might demand to introduce new circuit elements to the memory design. For example in the case under some certain conditions using single-ended sense amplifiers shown to be beneficial, there might be a need to design circuits to provide the required reference voltages for their operations. Consequently, the following are some key steps for the thesis and will be used as milestones or goals: • Investigating the possibility of using in-memory charge pump circuitry to provide local voltage boosting in desired memory nodes with the intention of maintaining acceptable R/W reliability in low power memories. Cares must be taken to avoid introducing unnecessarily extra area overhead to the memory layout. • Investigating and proposing sense amplifier circuitry which is more suitable for low voltage SRAM memories. • Implementing a voltage reference generator to be used for sense amplifier diversity schemes to improve detection reliability; e.g. using single-ended sense amplifier circuits in combination with a differential one to enhance memory cell read reliability.