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Showing result 11 - 15 of 24 essays matching the above criteria.
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11. An FPGA Implementation of Arbiter PUF with 4x4 Switch Blocks
University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)Abstract : Theft of services, private information, and intellectual property have become significant dangers to the general public and industry. Cryptographic algorithms are used for protection against these dangers. All cryptographic algorithms rely on secret keys that should be generated by an unpredictable process and securely stored. READ MORE
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12. Test and Repair of Reconfigurable On-chip Instrument Access Networks
University essay from Lunds universitet/Institutionen för elektro- och informationsteknikAbstract : As transistors in integrated circuits (ICs) are becoming smaller, faster and more, it has become harder to avoid malfunctioning. Embedded instruments are increasingly used to test, tune, and configure the transistors in ICs. IEEE Std.1149. READ MORE
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13. Reconfigurable Instrument Access Network with a Functional Port Interface
University essay from Lunds universitet/Institutionen för elektro- och informationsteknikAbstract : The ever-increasing need for higher performance and more complex functionality pushes the electronics industry to find a faster and more efficient way to test and debug an Integrated Circuit (IC). Currently, the IEEE Std. 1149.1, known as Joint Test Action Group (JTAG) is considered as state of the art by the industry. READ MORE
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14. Statistical Approach for the Design of Refresh-Free eDRAM with Retention Timing Constraint
University essay from Lunds universitet/Institutionen för elektro- och informationsteknikAbstract : In digital integrated circuits, memories are often a limiter for main performance, power and area. Over the past decade, integrated memories have gained dominance in terms of area and power cost. In applications like machine learning or image processing the area share can be above 80% consuming more than 50% of the total power budget. READ MORE
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15. A Technology Agnostic Approach for Standard-cell Layout Design Automation
University essay from Lunds universitet/Institutionen för elektro- och informationsteknikAbstract : The logic scaling following Moores law has reached a level where System on Chips (SoCs) commonly contains millions of standard cells. The sheer amount implies that even small optimizations on a standard cell can have a significant effect on the SoC performance. To ensure the performance of standard cells, many of these are hand-drawn. READ MORE
