Essays about: "Application-Specific Integrated Circuit ASIC"

Showing result 1 - 5 of 25 essays containing the words Application-Specific Integrated Circuit ASIC.

  1. 1. Novel Method of ASIC interface IP development using HLS

    University essay from Lunds universitet/Institutionen för elektro- och informationsteknik

    Author : Anestis Athanasiadis; Chandranshu Mishra; [2023]
    Keywords : High Level Synthesis; HLS; Untimed C ; Control logic; I3C; clock-accurate design; IP development; Technology and Engineering;

    Abstract : High-Level Synthesis(HLS) is a design methodology that enables designers to implement hardware from high-level coding languages, such as C, C++, or System C. It provides designers with the ability to convey their design at a higher level of abstraction, which allows more emphasis on an algorithm and functional aspects of design instead on low-level hardware details. READ MORE

  2. 2. Estimation of Voltage Drop in Power Circuits using Machine Learning Algorithms : Investigating potential applications of machine learning methods in power circuits design

    University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Author : Dimitrios Koutlis; [2023]
    Keywords : Voltage drop estimation; Application-specific Integrated Circuits ASICs ; Machine learning algorithms; XGBoost; Convolutional Neural Networks; Graph Neural Networks; Power circuit optimization; Uppskattning av spänningsfall; applikationsspecifika integrerade kretsar ASIC ; maskininlärningsalgoritmer; XGBoost; konvolutionella neurala nätverk; optimering av strömkretsar;

    Abstract : Accurate estimation of voltage drop (IR drop), in Application-Specific Integrated Circuits (ASICs) is a critical challenge, which impacts their performance and power consumption. As technology advances and die sizes shrink, predicting IR drop fast and accurate becomes increasingly challenging. READ MORE

  3. 3. Algorithmic Multi-Ported Memories Enabled Power-Efficient Pre-Distorter Design in ASIC

    University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Author : Xuying Shen; [2023]
    Keywords : Multi-ported memory; Digital Pre-distortion; Hardware design; ASIC; Power efficiency; Flerporterat minne; Digital Pre-distortion; Hårdvarudesign; ASIC; Effekteffektivitet;

    Abstract : The transition from the 5G to the 6G era is a pivotal juncture in contemporary wireless communication. Under such a circumstance, Digital Pre-Distortion (DPD) technology has established its significance as an effective method to linearize Power Amplifiers. READ MORE

  4. 4. Introducing Machine Learning in a Vectorized Digital Signal Processor

    University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Author : Linnéa Ridderström; [2023]
    Keywords : Digital Signal Processor DSP ; Application-Specific Integrated Circuit ASIC ; Machine Learning; Deep Learning; Convolutional Neural Network CNN ; Very Long Instruction Word VLIM ; Single Instruction Multiple Data SIMD ; Digital Signalprocessor DSP ; Applikation-Specifik Integrerad Krets ASIC ; Maskininlärning; Djupinlärning; Konvolutionella Neurala Nätverk CNN ; Very Long Instruction Word VLIW ; Single Instruction Multiple Data SIMD ;

    Abstract : Machine learning is rapidly being integrated into all areas of society, however, that puts a lot of pressure on resource costraint hardware such as embedded systems. The company Ericsson is gradually integrating machine learning based on neural networks, so-called deep learning, into their radio products. READ MORE

  5. 5. High Level Synthesis for ASIC and FPGA

    University essay from Lunds universitet/Institutionen för elektro- och informationsteknik

    Author : Malin Heyden; [2023]
    Keywords : HLS; high level synthesis; asic; fpga; catapult; filter; sfir; Technology and Engineering;

    Abstract : This thesis aims to evaluate the performance of Siemens’ High Level Synthesis (HLS) tool Catapult. HLS can be considered the next step up in abstraction level from writing traditional Register Transfer Level (RTL) code which is time consuming and error prone. READ MORE