Essays about: "Carry-chain"

Found 3 essays containing the word Carry-chain.

  1. 1. A 1.8 ps Time-to-Digital Converter (TDC) Implemented in a 20 nm Field-Programmable Gate Array (FPGA) Using a Ones-Counter Encoding Scheme with Embedded Bin-Width Calibrations and Temperature Correction

    University essay from Linköpings universitet/Datorteknik

    Author : Engström Sven; [2020]
    Keywords : time-to-digital; time-to-digital converter; TDC; 1.8 ps; field-programmable gate array; FPGA; 20 nm; Xilinx; Kintex; UltraScale; tapped delay line; TDL; taps; carry-chain; ones-counter; bit-counter; bubbles; wave-union; embedded; temperature correction;

    Abstract : This thesis investigates the use of field-programmable gate arrays (FPGAs) to implement a time-to-digital converter (TDC) with on-chip calibration and temperature correction.Using carry-chains on the Xilinx Kintex UltraScale architecture to create a tapped delay line (TDL) has previously been proven to give good time resolution. READ MORE

  2. 2. Adaptive TDC : Implementation and Evaluation of an FPGA

    University essay from Linköpings universitet/Datorteknik

    Author : Simon Andersson Holmström; [2015]
    Keywords : TDC; Carry-chain; FPGA; Zynq; Delay;

    Abstract : Time to digital converter (TDC) is a digital unit that measures the time interval between two events.This is useful to determine the characteristics and patterns of a signal or an event. In this thesis ahybrid TDC is presented consisting of a tapped delay line and a clock counter principle. READ MORE

  3. 3. Near threshold operation of 16-bit adders in 65nm CMOStechnology

    University essay from Linköpings universitet/Elektroniska komponenter; Linköpings universitet/Tekniska högskolan

    Author : Ravi Maddula; [2014]
    Keywords : RCA; MCCA; KSA; Linearity; Average Power; PDP; Operating Frequency; Optimisation;

    Abstract : The main objective of the thesis is to implement different architectures of 16-bit adders such as; Ripple CarryAdder (RCA), Manchester Carry Chain Adder (MCCA) and Kogge Stone Adder (KSA), in 65nm CMOS technology and to study their performance in terms of power, operating frequency and speed at near threshold operating regions. The performance of these adders are evaluated and compared with each other and a final conclusion is made as to which adder structure is more suitable for implementation in a 65nmtechnology for low power applications. READ MORE