Essays about: "Noc"

Showing result 6 - 10 of 43 essays containing the word Noc.

  1. 6. Design of the SiLago GNOC

    University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Author : Weiyao Tang; [2022]
    Keywords : Synchoros Blocks; SiLago models; Network on Chips; Routing Algorithm and Deadlock; Physical Design; Synchoros-block; SiLago-modeller; nätverk på chip; routingalgoritm och dödläge; fysisk design;

    Abstract : Synchoros VLSI design style can be an alternative choice to fit the increasing complexity of embedded multi-processor architectures. SiLago Block is part of the synchoros blocks, which can effectively reduce the cost of logic and physical synthesis as it is hardened and highly centralized details from each layer of metal. READ MORE

  3. 7. NoC for Versatile Micro-Code Programmable Multi-Core Processor Targeting Convolutional Neural Networks

    University essay from Linköpings universitet/Datorteknik

    Author : Mattias Evaldsson; [2021]
    Keywords : ;

    Abstract : This thesis investigates building a network-on-chip for a multi-core chip computing convolutional neural networks (CNNs) using Imsys processors in a tree architecture. The division of work on a multi-core chip is investigated. READ MORE

  4. 8. A Specification for Time-Predictable Communication on TDM-based MPSoC Platforms

    University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Author : Kelun Liu; [2021]
    Keywords : Communication; Time-Predictability; Network-on-Chip; Software Specification; Worst-Case Communication Time; Kommunikation; Tid Förutsägbarhet; Nätverk-på-Chip; MjukvaruSpecifikation; Kommunikationstid i Värsta Fall;

    Abstract : Formal System Design (ForSyDe) aims to bring the design of multiprocessor systems-on-chip (MPSoCs) to a higher level of abstraction and bridge the abstraction gap by transformational design refinement. The current research is focused on a correct-by-construction design flow, which requires design space exploration including formal models of computation and timepredictable platforms. READ MORE

  5. 9. Global clock distribution in the SiLago platform

    University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Author : Jordi Altayó; [2020]
    Keywords : ;

    Abstract : The extreme evolution of Very Large Scale Integration (VLSI) design has followed Moore’s law for the past decades, which predicts a doubling of the number of transistors that can be implemented on a chip every 18 months. However, tightly coupled with the evolution of the technology capabilities, the complexity during the implementation of such designs has also increased dramatically. READ MORE

  6. 10. Low Density Parity Check Encoder and Decoder on SiLago Coarse Grain Reconfigurable Architecture

    University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)

    Author : Weijiang Kong; [2019]
    Keywords : LDPC; CGRA; Reconfigurable architecture; VLSI design; ASIC; LDPC; CGRA; Konfigurerbar arkitektur; VLSI design; ASIC;

    Abstract : Low density parity check (LDPC) code is an error correction code that has been widely adopted as an optional error correcting operation in most of today’s communication protocols. Current design of ASIC or FPGA based LDPC accelerators can reach Gbit/s data rate. READ MORE