Essays about: "Riktlinje"
Showing result 11 - 15 of 65 essays containing the word Riktlinje.
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11. Mångfald av arter bland stadens träd : hur olika kommuner i Sverige arbetar med mångfald av trädarter i urbana miljöer
University essay from SLU/Dept. of Landscape Architecture, Planning and Management (from 130101)Abstract : Träden i staden fyller många viktiga funktioner, dels för stadens ekosystem och dess tillhandahållande av ekosystemtjänster, dels för bevarandet av biologisk mångfald. Träden bidrar med många effekter som skapar bättre klimat och livskvalitet i städerna, till exempel renare luft och behagligare lokalklimat. READ MORE
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12. Standardization of a modular on-trackgantry system
University essay from Blekinge Tekniska Högskola/Institutionen för maskinteknikAbstract : This thesis is an investigation of how a modular on-track gantry system intendedfor arc-welding robots can be standardized by using the existing product portfolio ofon-track gantry systems of a company.The company in this thesis have chosen to be anonymous, and will be referred toas the company. READ MORE
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13. An Embedded Software Design to Help Asthma Patients Inhale Medication Correctly
University essay from KTH/Skolan för kemi, bioteknologi och hälsa (CBH)Abstract : Managing the respiratory diseases could be hard for many patients. Usually patients use the inhaler to administrate medicine on a regular basis. Even though the inhaler guideline is well-accepted, most patients make mistakes. READ MORE
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14. Mechanical properties of viscose filament : Made from recycled cotton textile and softwood dissolving pulp
University essay from Karlstads universitet/Institutionen för ingenjörs- och kemivetenskaper (from 2013)Abstract : The textile industry is one of the largest industries in the world and it causes up to 10 % of the global greenhouse gas emissions. With large environmental issues of cotton- and oil-based textiles, other options are explored such as man-made fibers producing fibers like viscose and lyocell. READ MORE
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15. Validation of efficiency of formal verification methodology for verification closure
University essay from KTH/Skolan för elektroteknik och datavetenskap (EECS)Abstract : Application Specific Integrated Circuits (ASIC) and Field Programmable Gate Arrays (FPGA) verification is quite a time consuming phase in design flow cycle and it can be done using methodologies such as Universal Verification Methodology (UVM) and formal verification.The UVM methodology is simulation based verification where in the verifier will have to trigger the Design Under Test (DUT) manually by writing sequences which target different features of the DUT and the verification environment can also have verification directives such as assertions to spot design bugs. READ MORE